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SX1210
ADVANCED COMMUNICATIONS & SENSING
3.2.3. PLL Architecture
The crystal oscillator (XO) forms the reference oscillator of an Integer-N Phase Locked Loop (PLL), whose
operation is discussed in the following section. Figure 5 shows a block schematic of the SX1210 PLL. Here the
crystal reference frequency and the software controlled dividers R, P and S determine the output frequency of the
PLL.
÷75.(P i +1)+S i
PFD
LO
XO
÷(R i +1)
Fcomp
Vtune
XT_M
XT_P
LF_P
LF_M
VCO_P
VCO_M
VR_VCO
Figure 5: Frequency Synthesizer Description
The VCO tank inductors are connected on an external differential input. Similarly, the loop filter is also located
externally. However, there is an internal 8pF capacitance at VCO input that should be subtracted from the desired
loop filter capacitance.
The output signal of the VCO is used as the input to the local oscillator (LO) generator stage, illustrated in Figure 6.
The VCO frequency is subdivided and used in a series of up (down) conversions for transmission (reception).
LO1 Rx
LO
VCO Output
÷8
90°
I
Q
LO2 Rx
Receiver
LOs
Figure 6: LO Generator
3.2.4. PLL Tradeoffs
With an integer-N PLL architecture, the following criterion must be met to ensure correct operation:
The comparison frequency, Fcomp, of the Phase Frequency Detector (PFD) input must remain higher than six
times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison
frequency Fcomp. This is expressed in the inequality:
PLLBW ≤
Fcomp
6
However the PLLBW has to be sufficiently high to allow adequate PLL lock times
Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp ≈ 100 kHz
which will ensure suitable PLL stability and speed.
With the recommended Bill Of Materials (BOM) of the reference design of section 7.5.3, the PLL prototype is the
following:
64 ≤ R ≤ 169
S < P+1
PLLBW = 15 kHz nominal
Startup times and reference frequency spurs as specified.
Rev 2– Sept 8 , 2008
th
Page 14 of 73
www.semtech.com
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